Interconnects Beyond Copper, 1,000 CFETs, SK Hynix Next-Gen NAND, 2D Materials, and More

It’s an odd time in the chipmaking industry. On one hand, we are ramping into the biggest supercycle ever seen. Advanced logic, DRAM, NAND, customers can’t get enough, chipmakers can’t build capacity fast enough, and we may soon be limited by fab equipment supply. On the other hand, the rapid technology improvement in scaling, power consumption, chip cost, etc. have slowed to a crawl. Massive research efforts yield small incremental gains. As costs increase but improvements asymptote and scaling runs out of room at the bottom, it sometimes feels like Moore’s Law has become Moore’s Wall.

The good news is the semiconductor industry has a long history of making naysayers look stupid in the long run. There are plenty of innovations on the bench that are promising for the next decade and beyond. In this report, as with 2022, 2023, and 2024, we’ll cover highlights from IEDM 2025 to find out what the future of chipmaking might look like.

With memory prices exploding, 3D NAND technology is suddenly relevant again. We’ll look at the technology and competitiveness of SK Hynix’s latest V9 NAND, Samsung’s use of Mo to improve its existing V9 products, and a big innovation that we may see in future production from SK Hynix. For advanced logic, we’ll look at interconnect metals beyond Cu, the potential of 2D materials to replace Si in transistors, and the progress in CFET, the next big inflection after gate-all-around.

3D NAND

NAND scaling is critically relevant right now, as demand is spiking but there is no cleanroom space for building out capacity. Memory producers are limited to upgrading existing lines, so their supply is constrained by how dense their upgraded process is. For leading fabs, this is a 3xx-layer 3D NAND process, which yields on the order of 20-30 Gb/mm² of memory. That pencils out to 30+ TB of memory on a single 12” wafer (note the difference between (b)its and (B)ytes in these abbreviations).

3D NAND: Hynix 321 Layer

In the case of SK Hynix, the 321-layer process has 44% more memory per wafer than the previous generation 238-layer technology. If you are constrained by cleanroom space and by extension the number of wafers you can produce, 44% more memory on each of those wafers makes upgrades an obvious choice.

We’ve written in detail about NAND scaling methods, as a quick recap:

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