Wikipedia Deep Dive

10 nm process

12 min read

The Great Nanometer Lie

Here's a dirty secret the semiconductor industry doesn't advertise: when Intel or Samsung or any other chipmaker announces their latest "10 nanometer" processor, not a single feature on that chip actually measures ten nanometers.

Not the transistor gates. Not the metal wires connecting them. Not the spacing between components. Nothing.

The number is pure marketing fiction—and has been since at least 1997. What was once a genuine measurement describing the physical dimensions of transistor features has devolved into something more like a brand name, a way for companies to signal "this is newer and better than our previous chips" without committing to any actual specification.

How We Got Here

To understand this peculiar state of affairs, we need to step back and ask: what does a "process node" even mean?

In the early days of semiconductor manufacturing, the number referred to the gate length of a transistor—the critical dimension that determines how small you can make the switches that perform computations. A "one micron" process in the 1980s meant transistors with gates roughly one millionth of a meter long. As engineers shrunk these features, the numbers got smaller: 800 nanometers, 500, 350, 250, 180, 130, 90, 65, 45, 32, 22...

Each step down promised faster switching speeds, lower power consumption, and the ability to cram more transistors onto each chip. This was the engine driving Moore's Law, the famous observation that the number of transistors on integrated circuits doubles roughly every two years.

But somewhere along this path—around the 90 or 65 nanometer nodes—the relationship between the marketing number and actual transistor dimensions started to fray. Companies discovered they could claim a new "node" by improving transistor density or performance without necessarily shrinking the physical features proportionally. The numbers became aspirational rather than descriptive.

The Wild West of Process Names

By the time we reached the so-called "10 nanometer" generation, the disconnect had become almost absurd.

GlobalFoundries, a major chip foundry, labeled certain processes as "7 nanometer"—yet when engineers examined the actual transistor dimensions, they were essentially identical to what Intel called its "10 nanometer" technology. Same physical structures, different marketing names.

Meanwhile, both Taiwan Semiconductor Manufacturing Company (TSMC) and Samsung shipped chips they called "10 nanometer," but these were measurably less dense than Intel's "10 nanometer" chips. In terms of how many transistors actually fit in a given area, the TSMC and Samsung offerings sat somewhere between Intel's "14 nanometer" and "10 nanometer" processes.

This isn't mere pedantry. For anyone trying to compare chips from different manufacturers—or understand what they're actually buying—the naming chaos creates genuine confusion. A "7 nanometer" chip from one company might be roughly equivalent to a "10 nanometer" chip from another. The numbers have become unreliable signals.

What Actually Matters: Transistor Density

If the nanometer number is meaningless, what should we pay attention to?

The most useful metric is transistor density: how many transistors can you pack into each square millimeter of silicon? This directly determines how complex a chip you can build at a given size, which in turn affects performance, power efficiency, and manufacturing cost.

Here's a concrete example. When Apple announced its A11 processor in September 2017—the chip that powered the iPhone 8 and iPhone X—it contained 4.3 billion transistors on a die measuring 87.66 square millimeters. That works out to roughly 49 million transistors per square millimeter, manufactured by TSMC using what they called their "10 nanometer" FinFET process.

Three years later, Nvidia released its GeForce 30 series graphics cards using Samsung's "8 nanometer" process, achieving a density of about 44.56 million transistors per square millimeter. Despite the smaller-sounding number, the Nvidia chips were actually less dense than Apple's earlier "10 nanometer" design.

This illustrates why transistor density matters more than the marketing node: smaller numbers in the name don't guarantee more transistors or better performance.

The FinFET Revolution

One technical detail that does unite all these "10 nanometer" processes is their fundamental transistor architecture: they all use FinFETs.

The name stands for "fin field-effect transistor," and it represents one of the most significant innovations in chip design over the past two decades. To understand why, picture a traditional planar transistor as a tiny electrical switch lying flat on the silicon surface. Current flows through a channel, and a gate electrode sits above it, controlling whether the switch is on or off.

The problem is that as you shrink this structure, the gate loses control. Current starts leaking through even when the transistor is supposed to be off, wasting power and generating heat. By the time engineers reached features just a few tens of nanometers wide, planar transistors were becoming unmanageable.

The FinFET solution was elegant: stand the channel up on its edge, forming a thin vertical "fin" of silicon. Now the gate electrode can wrap around three sides of the channel instead of just sitting on top. This dramatically improves control, reducing leakage and allowing transistors to switch faster while using less power.

Intel pioneered commercial FinFETs with their "22 nanometer" process in 2012. By the "10 nanometer" generation, every major manufacturer had adopted the architecture. It was no longer optional—planar transistors simply couldn't scale further.

A Timeline of "10 Nanometer" Production

The race to "10 nanometer" production reveals the competitive dynamics of the semiconductor industry—and the very different strategies companies pursued.

Samsung moved first, in a sense. In April 2013, they announced mass production of flash memory chips using what they called a "10 nanometer-class" process. But this terminology was deliberately vague; according to industry analysts, Samsung defined "10 nanometer-class" as anything between 10 and 20 nanometers. It was more of a marketing category than a precise specification.

For logic chips—the processors that do actual computation rather than just storing data—Samsung began "10 nanometer" production in October 2016. Their first major product was the Exynos processor powering the Galaxy S8 smartphone, which shipped in April 2017.

TSMC followed a similar timeline, beginning commercial "10 nanometer" production in early 2016 with high-volume manufacturing ramping up in 2017. Apple became their flagship customer, with the A10X chip (powering the 2017 iPad Pro) and then the A11 (for that year's iPhones) both manufactured on the process.

Intel's journey was far rockier.

Intel's 10 Nanometer Troubles

In 2008, Pat Gelsinger—then Intel's Chief Technology Officer, and now the company's CEO—expressed confidence that Intel saw "a clear way" to 10 nanometer technology. At the time, Intel was the undisputed leader in manufacturing process technology, typically running a generation ahead of competitors.

That confidence proved premature.

Intel originally planned to begin "10 nanometer" production around 2016, following the same two-year cadence that had defined Moore's Law for decades. But yield problems—meaning too many defective chips coming off the production line—forced repeated delays.

In April 2018, Intel announced that volume production of mainstream "10 nanometer" processors wouldn't happen until sometime in 2019. By July, they'd narrowed it down to the holiday season. In the meantime, they shipped a limited "10 nanometer" mobile chip, but only in China and with much of the chip's functionality disabled—essentially a salvage part from their troubled production lines.

The delays were embarrassing and costly. While Intel struggled, TSMC and Samsung leapfrogged ahead to what they called "7 nanometer" technology. Intel, once the process technology leader, found itself a generation behind.

The Node That Never Was

Not everyone even bothered with "10 nanometer."

GlobalFoundries, after evaluating the technology, decided to skip the node entirely. Their reasoning was pragmatic: "10 nanometer" appeared likely to be a short-lived transition technology, quickly superseded by "7 nanometer." Rather than invest billions in a process that might only be relevant for a year or two, they chose to jump directly to the next generation.

TSMC reached a similar conclusion from the opposite direction. They did produce "10 nanometer" chips, but treated the node as transitional, mainly serving Apple during 2017 and early 2018 before moving their attention to "7 nanometer."

This highlights an important reality about semiconductor manufacturing: process nodes require enormous capital investments—new equipment, new facilities, years of engineering development. Companies must carefully judge which nodes are worth the investment and which can be skipped. Not every step on the marketing ladder corresponds to a genuine technological advance worth billions of dollars.

The Numbers Behind the Numbers

If you want to cut through the marketing fog, there are some actual measurements worth examining.

One is "gate pitch" (also called "contacted poly pitch" or CPP)—the distance from one transistor gate to the next. Samsung reported their "10 nanometer" process as having a 64 nanometer gate pitch. So did TSMC. Note that both are far larger than the "10 nanometer" name suggests.

Another is "interconnect pitch" (or "minimum metal pitch")—the distance between the tiny metal wires that connect transistors. Samsung reported 48 nanometers; TSMC reported 42 nanometers. Again, not even close to ten.

But here's where it gets even murkier: independent analysis by TechInsights, a firm that specializes in reverse-engineering chips, found that even these officially reported values were inaccurate. The real dimensions differed from what the companies claimed.

This isn't necessarily deception—measurement methodologies vary, and companies may measure slightly different things. But it underscores how difficult it is to make meaningful comparisons based on any single number.

The Memory Industry's Different Dictionary

Confusingly, the memory chip industry uses "10 nanometer" terminology too—but means something completely different.

For Dynamic Random Access Memory (DRAM), the dominant type of computer memory, "10 nanometer-class" refers to the half-pitch of the memory cell array: half the distance between identical repeating features. This at least has some relationship to actual dimensions, but it's measuring different structures than logic chip "process nodes."

As of 2020, "10 nanometer class" DRAM encompassed three generations with wonderfully cryptic names:

1x nanometer (first generation): features sized between 19 and 17 nanometers
1y nanometer (second generation): features between 16 and 14 nanometers
1z nanometer (third generation): features between 13 and 11 nanometers

Samsung introduced third-generation "1z" DRAM around 2019. Looking ahead, they named their fourth generation "D1a" and the fifth "D1b." Micron, another major memory manufacturer, preferred Greek letters: "D1α" and "D1β."

The naming schemes have become so divorced from physical reality that companies are essentially inventing new alphabets to describe their progress.

The Lithography Revolution Looming

Throughout most of the "10 nanometer" era, chips were manufactured using deep ultraviolet (DUV) lithography—the technology that etches circuit patterns onto silicon using light. But pushing DUV to ever-smaller features required increasingly elaborate tricks, including "triple patterning," where the same layer must be exposed and etched three separate times with slightly offset patterns.

This is slow, expensive, and introduces more opportunities for defects. It's one reason Intel struggled so badly with "10 nanometer" yields.

The industry's long-awaited salvation was extreme ultraviolet (EUV) lithography, which uses much shorter wavelengths of light to pattern finer features in a single exposure. Samsung initially produced its "1z" DRAM without EUV, but subsequent production adopted the technology.

EUV has now become essential for the most advanced nodes, though its own journey to production took decades and billions of dollars of development.

What Does This Mean for Chip Buyers?

For consumers and businesses purchasing devices with these chips inside, the practical implications are straightforward: ignore the nanometer numbers.

Instead, look at actual benchmarks: processing speed, power consumption, battery life, thermal performance. These real-world measurements tell you far more about a chip's capabilities than any "10 nm" or "7 nm" label.

If you're evaluating competing products—say, laptops with Intel versus AMD processors, or phones with Qualcomm versus Apple silicon—the manufacturing process node tells you almost nothing useful. A chip on a "worse" node might still outperform one on a "better" node through superior architecture, better software optimization, or smarter thermal design.

The Deeper Problem

The nanometer naming mess reflects a broader challenge facing the semiconductor industry: Moore's Law is winding down.

For decades, the industry could rely on steady improvements from shrinking transistors. Smaller meant faster, cheaper, more power-efficient. The path forward was clear—just keep shrinking.

But as we approach atomic scales, that path is ending. You can't make a transistor smaller than a few atoms. Physical limits—quantum tunneling, heat dissipation, manufacturing precision—are increasingly binding constraints rather than theoretical concerns.

The marketing fog around process nodes may partly be an attempt to maintain the appearance of progress even as the underlying physics becomes less cooperative. If you can't actually shrink transistors as fast as before, you can at least shrink the number in your marketing materials.

This doesn't mean progress has stopped. Chipmakers continue finding ways to improve performance through three-dimensional stacking, better packaging that connects multiple chips together, specialized accelerators for particular workloads, and software optimizations. But the simple story of "smaller number equals better chip" has become a relic of an earlier, simpler era.

Looking Forward

The next chapters of this story are already being written. Intel, after years of stumbles, has embarked on an ambitious plan to regain process leadership with nodes they now call "Intel 4," "Intel 3," and eventually "Intel 18A" and "14A"—finally abandoning the pretense that these numbers represent nanometers at all.

TSMC and Samsung continue their own advancement, with "3 nanometer" and "2 nanometer" processes in development or production. The numbers will keep getting smaller even as their relationship to physical reality grows ever more tenuous.

Perhaps someday the industry will adopt more honest nomenclature—transistor density figures, power efficiency metrics, or simply generation numbers without misleading dimensional claims. Until then, understanding that "10 nanometer" is essentially a brand name, not a measurement, is the first step toward making sense of the bewildering world of modern semiconductors.